Technical Features
Thermal Throttling
Industrial SSD are equipped with built-in high-precision temperature sensors, combined with firmware settings, to achieve phased throttling. The independent firmware within the control chip enables the controller to monitor the SSD temperature data in real time, perform dynamic temperature adjustments based on data reliability, and transmit the data back in real time.
Garbage Collection (GC)
The Garbage Collection (GC) mechanism is used to clean up invalid data in SSD, freeing up space for new data writes. An excellent GC algorithm or mechanism can effectively enhance both the lifespan and steady-state performance of the SSD.
pSLC
pSLC technology is a technique that emulates MLC or multi-level cell flash memory as SLC (single-level cell). Through this technology, TLC/MLC flash memory can achieve a lifespan, reliability, and performance close to that of SLC flash memory.
TRIM
A function used to optimize the SSD garbage collection process by informing the SSD in advance which blocks are no longer needed, thereby speeding up space release, reducing WAF, and extending the SSD's lifespan.
pSLC Partition
Supports creating a logical partition for storing important data. Users can specify a special LBA range via protocol commands, and data subsequently written to this LBA range will always be stored in SLC mode, ensuring high reliability.
In-drive RAID
Within the SSD, RAID is implemented by leveraging the physical structure and characteristics of each NAND flash die to address scenarios where data reliability is compromised due to various factors, thereby safeguarding user data.
Partition-based Concurrency Control
Supports multiple logical partitions: Boot, RPMB, GP, User, etc. for concurrent access to independent areas.
Concurrency advantages:
During system startup: Boot partition read + User partition preload in parallel.
In security scenarios: RPMB authentication + User data read/write do not block each other.
HS400
Employing DDR (Double Data Rate) technology, data is transmitted on both the rising and falling edges of the clock. An 8-bit parallel bus combined with a Data Strobe signal enhances signal integrity. The theoretical read/write speed reaches up to 400MB/s, while the actual sustained read/write speed ranges from 250 to 350 MB/s, meeting the demands of 4K video recording, fast application startup, and more.
Command Queuing
Random read/write performance improved by 30-50%.
Reduces CPU interrupt overhead and improves system response speed.
Sequential/Random Data Separation
The firmware algorithm identifies sequential and random data and allocates them into different data streams at the algorithm layer, improving performance, reducing WAF (Write Amplification Factor), and extending lifespan.
